The exponential increase in computing performances of digital integrated circuits (ICs) fundamentally modified our everyday’s life in numerous domains (consumer, business, medical, industrial). Nowadays these circuits feature several millions of transistors, which results in a high design complexity. Moreover, they usually integrate various IP blocks (memories, CPU cores, PLL) from external vendors, leading to digital systems-on-chip (SoCs). Therefore, digital circuit design requires the use of methodologies and computer-aided design (CAD) tools within a systematic design flow. In this course, we will study the automatic synthesis of very-large scale integration (VLSI) digital ICs (microprocessors, ASICs and SoCs) using a top-down synthesis flow from system design to its translation in a logic-gate netlist to its physical implementation on a silicon die (layout).